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1 1.5a, rad hard, positive, high voltage ldo isl75052seh the isl75052seh is a radiation hardened, single output ldo specified for an output current of 1.5a. the device operates from an input voltage range of 4.0v to 13.2v and provides for output voltages of 0.6v to 12.7v. the output is adjustable based on a resistor divider setting. dropout voltages as low as 75mv (at 0.5a) typical can be realized using the device. this allows the user to improve the system efficiency by lowering v in to nearly v out . the enable feature allows the part to be placed into a low shutdown current mode of 165 a ( typ). when enabled the device operates with a low ground current of 11ma (typ), which provides for operation with low quiescent power consumption. the device has superior transi ent response and is designed keeping single event effects in mind . this results in reduction of the magnitude of set seen on th e output. there is no need for additional protection diodes and filters. comp pin is provided to enable the use of external compensation. this is achieved by connecting a resistor and capacitor from comp to ground. the device is stable with tantalum capacitors as low as 47f (kemet t525 series) and provides excellent regulation all the way from no load to full load. the programmable soft-sta rt allows one to program the inrush current by means of the decoupling capacitor used on the byp pin. the ocp pin allows the sh ort circuit output current limit threshold to be programmed by me ans of a resistor from ocp pin to gnd. the ocp setting range is from a 0.16a min to 3.2a max. the resistor sets the constant current threshold for the output under fault conditions. the therma l shutdown disables the output if the device temperature exceed s the specified value, it will subsequently enter a on/off cycle till the fault is removed. applications ? ldo regulator for space power systems ? dsp, fpga and p core power supplies ? post regulation of smps and down hole drilling features ?dla smd 5962-13220 ? input supply range 4.0v to 13.2v. ? output current up to 1.5a at a t j = +150c ? best in class accuracy 1.5% - over line, load and temperature ? ultra low dropout: - 75mv dropout (typ) @ 0.5a - 225mv dropout (typ) @ 1.5a ? noise of 100v rms (typ) between 300hz to 300khz ? set mitigation with no added filtering/diodes ? shutdown current of 165 a (typ) ? externally adjustable output voltage ? psrr 65db (typ) @ 1khz ? en able and pg ood feature ? programmable soft-start/in-rush current limiting ? adjustable overcurrent protection ? over-temperature shutdown ? stable with 47f min tantalum capacitor ? package 16 ld flat pack ? radiation environment - high dose rate (50-300rad(si)/s) . . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s). . . . . . . . . . . . 100krad(si)* - set/sel/seb . . . . . . . . . . . . . . . . . . . . . . . . .. 86 mev.cm2/mg *product capability established by initial characterization. the "eh" version is acceptance tested on a wafer-by-wafer basis to 50krad(si) at low dose rate. related literature see an1850 , "isl75052seh evaluation board user's guide" see an1851 , "see testing of the isl75052seh" see an1852 , "radiation report of the isl75052seh" figure 1. typical application 15.8k 4.87k 2.2k 2.2n vout 2.5v 300 en vin 1nf pg vin 3,4,5 isl75052seh 16 15 14 13 8 10 12 9 vout vin ocp pg comp vccx gnd en adj byp 1,2 22k 22k 0.1f 0.1f 200f 0.1f 0.1f 200f figure 2. dropout vs i out i load (a) dropout (v) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 0.5 1.0 1.5 2.0 +125c +150c 25c caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners may 29, 2013 fn8456.0
isl75052seh 2 fn8456.0 may 29, 2013 block diagram reference bias uvlo current limit thermal shutdown delay gnd pg adj en vin power pdmos vout comp byp 3.8v ldo vccx ocp 540mv 600mv typical applications figure 3. pg 4.87k 15.8k 2.2k vccx 10k en vin 1nf 22k 1 3 2 isl75052seh 16 15 14 13 12 11 10 9 4 5 6 7 8 byp vout vout vin vin vin nc nc ocp adj en gnd gnd comp pg vccx nc = no connect pin can be connected to either vin or gnd vout = 2.5v 300 0.1f 100f 100f 0.1f 0.1f 100f 0.1f 100f 2.2nf
isl75052seh 3 fn8456.0 may 29, 2013 pin configuration isl75052seh (16 ld cdfp) top view 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 vout vout vin vin vin nc nc ocp byp adj en gnd comp pg vccx tmode dotted line shows metal bottom pin descriptions pin number pin name description esd circuit 3, 4, 5 vin input supply pins. circuit 1 10 pg this pin is logic high when v out is in regulation signal. a logic low defines when v out is not in regulation. circuit 2 13 gnd gnd pin. pin 13 is also connected to the metal lid of the package. circuit 2 9 vccx the 3.8v internal bus is pinned out to ac cept a decoupling capacitor. connect a 0.1f ceramic capacitor from vccx pin to gnd. circuit 2 1, 2 vout output voltage pins. circuit 1 12 comp add compensation capacitor & resi stor between comp and gnd. circuit 2 15 adj adj pin allows v out to be programmed with an external resistor divider. circuit 2 6, 7 nc no connect. may be grounded if needed. circuit 2 16 byp connect a 0.1f capacitor from byp pin to gnd, to filter the internal vref. circuit 2 8 ocp ocp pin allows the current limit to be programmed with an external resistor. circuit 2 14 en v in independent chip enable. ttl and cmos compatible. circuit 2 11 tmode test mode pin, must be connected to gnd. circuit 2 bottom metallization the metal surface on the bottom surface of the package is floating. for mounting instructions see ?bottom metal mounting guidelines? on page 8. circuit 2 pad gnd esd circuit 1 esd_cl_12v pad gnd esd_rc_7v esd circuit 2
isl75052seh 4 fn8456.0 may 29, 2013 ordering information ordering number internal mkt. number part marking temp range (c) package (rohs compliant) pkg dwg. # 5962r1322001vxc isl75052sehvfe q 5962r13 22001vxc -55 to +125 16 ld cdfp k16.e 5962r1322001v9a isl75052sehvx -55 to +125 die isl75052sehf/sample isl75052sehx/sample -55 to +125 die sample isl75052sehfe/proto isl75052sehfe/proto isl75052 sehfe /proto -55 to +125 16 ld cdfp k16.e isl75052sehev1zb evaluation board note: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations.
isl75052seh 5 fn8456.0 may 29, 2013 absolute maximum rating s thermal information v in relative to gnd without ion beam (note 2) . . . . . . . . . . -0.3 to +16.0v v in relative to gnd under ion beam (note 2) . . . . . . . . . . . -0.3 to +14.7v v out relative to gnd (note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +14.7v pg,en,ocp/adj,comp,refin,refout relati ve to gnd (note 2) . . . -0.3 to +6.5vdc recommended operating conditions (notes 3) ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-55c to +125c junction temperature (t j ) (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . .+150c v in relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0v to 13.2v v out range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5v to 12.7v pg, en, ocp/adj relative to gnd . . . . . . . . . . . . . . . . . . . . . . . .0v to +5.5v thermal resistance (typical) ja (c/w) jc (c/w) 16 ld cdfp package (notes 5, 6) . . . . . . . 26 4.5 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp radiation information maximum total dose high dose(dose rate = 50 - 300radsi/s) . . . . . . . . . . . .100 krads (si) low dose(dose rate = 10milliradsi/s) (note 4) . . . . . . 100 krads (si) set (v out within 5% during events . . . . . . . . . . . . . . . .86mev/mg/cm 2 sel/b (no latchup/burnout . . . . . . . . . . . . . . . . . . . . . . . . 86mev/mg/cm 2 the output capacitance used for see testing is 2x100f for c in and c out , 100nf for bypass caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. extended operation at these conditions may compromise reliabi lity. exceeding these limits will result in damage. recommended operating conditions define limits where specifications are guaranteed. 3. refer to ?bottom metal mounting guidelines? on page 8. 4. product capability established by initial characterization. the "eh" version is acceptance tested on a wafer by wafer basis t o 50 krad(si) at low dose rate. 5. ja is measured in free air with the comp onent mounted on a high effective thermal conductivity test board with ?direct attach? features. see techbrief tb379 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. electromigration specification defined as lifetime average ju nction temperature of +150c where max rated dc current = lifetime average current. electrical specifications unless otherwise noted, all parameters are guaranteed over the following specified conditions: v in =v out +0.5v, v out = 4.0v, c in = c out = 2x100f 60m , kemet type t541x107n025ah or equivalent, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?applications information? on p age 7 of the data sheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j =t a defines guaranteed limits. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics dc output voltage accuracy v out v out resistor adjust to: 2.5v and 5.0v v out = 2.5v, 4.0v < v in < 5.0v; 0a < i load < 1.5a, t j = -55c to +125c -1.5 0.2 1.5 % v out = 2.5v, 4.0v < v in < 5.0v; 0a < i load < 1.5a, t j = +25c, post rad. -2.0 0.2 2.0 % v out = 5.0v, 5.5v < v in < 6.9v; 0a < i load < 1.5a, t j = -55c to +125c -1.5 0.2 1.5 % v out = 5.0v, 5.5v < v in < 6.9v, 0a < i load < 1.5a, t j = +25c, post rad. -2.0 0.2 2.0 % v out resistor adjust to: 10.0v v out = 10.0v, 10.5v < v in < 13.2v, i load = 0a, t j =-55c to +125c -1.5 0.2 1.5 % v out = 10.0v, 10.5v < v in < 13.2v, i load = 0a, t j = +25c, post rad. -2.0 0.2 2.0 % v out = 10.0v, v in = 10.5v, i load = 1.5a, v in =13.2v, i load = 1.0a, t j = -55c to +125c -1.5 0.2 1.5 % v out = 10.0v, v in = 10.5v; i load =1.5a, v in =13.2v, i load = 1.0a, t j = +25c, post rad. -2.0 0.2 2.0 %
isl75052seh 6 fn8456.0 may 29, 2013 vccx pin v vccx t j = -55c to +125c; 4v < v in < 13.2v; i load =0a ; 3.7 3.9 4.1 v adj pin v adj t j = -55c to +125c 591 600 609 mv adj pin v adj t j = 25c, post rad 588 600 612 mv byp pin v byp 4.0v < v in < 13.2v; i load =0a , t j = -55c to +125c 588 600 612 mv dc input line regulation 4.0v < v in < 13.2v, v out = 2.5v 1 8 mv dc input line regulation 5.5v < v in < 13.2v, v out = 5.0v 1 20 mv dc input line regulation 10.5v < v in < 13.2v, v out = 10.0v 1 10 mv dc output load regulation v out = 2.5v; 0a < i load < 1.5a, v in = 4.0v 0.3 9 mv dc output load regulation v out = 5.0v; 0a < i load < 1.5a, v in = 5.5v 1.3 18 mv dc output load regulation v out = 10.0v; 0a < i load < 1.5a, v in = 10.5v 0.1 36 mv adj input current v adj = 0.6v 1 a ground pin current i q v out = 2.5v; i load = 0a, 4.0v < v in < 13.2v 6 10 ma ground pin current i q v out = 2.5v; i load = 1.5a, 4.0v < v in < 13.2v 8 12 ma ground pin current i q v out = 10.0v, i load = 0a, 11.0v < v in < 13.2v 15 20 ma ground pin current i q v out = 10.0v, i load = 1.5a, 11.0v < v in < 13.2v 20 25 ma ground pin current in shutdown i shdnl enable pin = 0v, v in = 4.0v 70 120 a ground pin current in shutdown i shdnh enable pin = 0v, v in = 13.2v 165 300 a dropout voltage (note 10) v do i load = 0.5a, v out = 3.6v and 12.7v 75 160 mv dropout voltage (note 10) v do i load = 1.0a, v out = 3.6v and 12.7v 150 300 mv dropout voltage (note 10) v do i load = 1.5a, v out = 3.6v and 12.7v 225 400 mv output short circuit current for 16 ld fp iscl v out set = 4.0v, v out + 0.5v < v in < 13.2v, r set = 3k, note 12) 0.16 0.24 0.32 a output short circuit current for 16 ld fp isch v out set = 4.0v, v out + 0.5v < v in < 13.2v, r set = 300 , note 12) 1.6 2.4 3.2 a thermal shutdown temperature (note 9) tsd v out + 0.5v < v in < 13.2v 154 175 196 c thermal shutdown hysteresis (rising threshold) (note 9) tsdn v out + 0.5v < v in < 13.2v 25 c ac characteristics input supply ripple rejection (note 9) psrr v p-p = 300mv, f = 1khz, i load = 1.5a; v in =4.9v, v out = 4.0v 55 65 db input supply ripple rejection (note 9) psrr v p-p = 300mv, f = 120hz, i load = 5ma; v in =4.9v, v out = 2.5v 60 70 db input supply ripple rejection (note 9) psrr v p-p = 300mv, f = 100khz, i load = 1.5a; v in = 4.9v, v out = 4.0v 40 50 db phase margin, (note 9) pm v out = 2.5v, 4.0v and 10v, c out = 2x100f, r comp =22k, c comp = 1nf 50 gain margin, (note 9) gm v out = 2.5v, 4.0v and 10v c out = 2x100f, r comp = 22k, c comp = 1nf 10 db output noise voltage, (note 9) i load = 10ma, bw = 300hz < f < 300khz, bypass to gnd capacitor = 0.2f 100 v rms electrical specifications unless otherwise noted, all parameters are guaranteed over the following specified conditions: v in =v out +0.5v, v out = 4.0v, c in = c out = 2x100f 60m , kemet type t541x107n025ah or equivalent, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?applications information? on p age 7 of the data sheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j =t a defines guaranteed limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl75052seh 7 fn8456.0 may 29, 2013 applications information input voltage requirements this rh ldo will work from a v in in the range of 4.0v to 13.2v. the input supply can have a tolerance of as much as 10% for conditions noted in the specification table. the minimum guaranteed input voltage is 4.0v. however, due to the nature of an ldo, v in must be some margin higher than the output voltage plus dropout at the maximum rate d current of the application if active filtering (psrr) is expected from v in to v out . the dropout spec of this family of ldos ha s been generously specified in order to allow design for efficient operation. external capacitor requirements general guideline external capacitors are required for proper operation. careful attention must be paid to layo ut guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor it is recommended to use a combination of tantalum and ceramic capacitors to achieve a good volume to capacitance ratio. the recommended combination is a 2x100f 60m rated, kemet t541 series tantalum capacitor, in parallel with a 0.1f mil-prf-49470 ceramic capacitor to be connected to v out and ground pins of the ldo with pc b traces no longer than 0.5cm. input capacitor it is recommended to use a combination of tantalum and ceramic capacitors to achieve a good capacitance to volume ratio. the recommended combination is a 2x100f 60m rated, kemet t541 series tantalum capacitor in parallel with a 0.1f mil-prf-49470 ceramic capacitor to be connected to v in and ground pins of the ldo with pc b traces no longer than 0.5cm. current limit protection the rh ldo incorporates protection against overcurrent due to any short or overload condition applied to the output pin. the current limit circuit performs as a constant current source when the output current exceeds the cu rrent limit threshold which can be adjusted by means of a resi stor connected between the ocp device start-up characteristics enable pin characteristics turn-on threshold 4.0v < v in < 13.2v 0.5 0.8 1.2 v enable pin leakage current v in = 13.2v, en = 5.5v 1 a enable pin propagation delay (en step 1.2v to v out = 100mv) v in = 4.5v, v out = 4.0v, i load = 1.5a, c out = 22f, c byp = 0.2f 0.5 1.0 ms enable pin turn-on delay (en step 1.2v to pgood) v in = 4.5v, v out = 4.0v, i load = 1.5a, c out = 2x100f, c byp = 0.2f 1.4 3.0 ms enable pin turn-on delay (en step 1.2v to pgood) v in = 4.5v, v out = 4.0v, i load = 1.5a, c out = 22f, c byp = 0.2f 1.1 2.5 ms hysteresis (falling threshold) 4.0v < v in < 13.2v 75 170 mv pg pin characteristics v out error flag rising threshold 83 88 94 %v out v out error flag falling threshold 80 86 91 %v out v out error flag hysteresis 1.75 2.5 %v out error flag low voltage i sink = 1ma 5 100 mv error flag low voltage i sink = 10ma 5 400 mv error flag leakage current v in = 13.2v, pg = 5.5v 1 a 8. parameters with bold face min and/or max limits are 100% tested at -55c, 25c and 125c. 9. limits established by characteriza tion and are not production tested. 10. dropout is defined by the difference in supply v in and v out when the supply produces a 2% drop in v out from its nominal value. 11. refer to thermal package guidelines in ?b ottom metal mounting guidelines? on page 8.. 12. ocp recovery overshoot should be within 4% of the nominal vout setpoint. 13. set performance of <5% at let = 86mev.cm2/mg has been evaluated at v out = >2.5v with c in = c out = 2x100f 10v 60m in parallel with 0.1f cdr04 x7r capacitor. capacitor on byp = 0.1f cdr04 x7r. electrical specifications unless otherwise noted, all parameters are guaranteed over the following specified conditions: v in =v out +0.5v, v out = 4.0v, c in = c out = 2x100f 60m , kemet type t541x107n025ah or equivalent, t j = +25c, i l = 0a. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?applications information? on p age 7 of the data sheet and tech brief tb379 . boldface limits apply over the operating temperature range, -55c to +125c. pulse load techniques used by ate to ensure t j =t a defines guaranteed limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl75052seh 8 fn8456.0 may 29, 2013 pin and gnd. if the short or overload condition is removed from v out , then the output returns to normal voltage mode regulation. in the event of an overload condition the ldo will begin to cycle on and off due to the die temperature exceeding thermal fault condition. however, one may never witness thermal cycling if the heatsink used for the package can keep the die temperature below the limits specified for thermal shutdown. the rocp can be calculated using the equation: where: r ocp = the ocp resistor value in ohms. i ocp = the required ocp threshold in amps. esd clamps the esd_cl_12v esd clamps brea k down at nominally 17v. the esd_rc_7v clamps break down at nominally 7.5v with a tolerance of 10%. the pg pin has a diode to gnd. the vout pin has a diode to vin (see ?pin descriptions? on page 3). comp pin this pin helps compensate the device for various load conditions. for 4.0v < vin < 6.0v use rcomp = 40k and ccomp = 1nf. for 6v < vin < 13.2v use rcomp = 40k and ccomp = 4.7nf. the max current of the comp pin when shorted to gnd is 160a. undervoltage lockout the undervoltage lockout functi on detects when vccx exceeds 3.2v. when that level is reached, the ldo feedback loop is closed and the ldo can begin regu lating. this is achieved by freeing the byp net to charge up and act as a reference voltage to the ea. prior to that happening, the ldo power pmos device is clamped off. bottom metal electrical potential the package bottom metal is elec trically isolated and unbiased. the bottom metal may be electrical ly connected to any potential which offers the best thermal pa th through conductive mounting materials (conductive epoxy, solder, etc.) or may be left unbiased through the use of electrically non-conductive mounting materials (non-conductive epoxy, sil-pad, kapton film, etc.). bottom metal mounting guidelines the package bottom is a solderable metal surface. the following jesd51-5 guidelines may be used to mount the package: ? place a thermal land on the pcb under the bottom metal. ? the land should be approximately the same size to 1mm larger than the 0.19x0.41inch bottom metal. ? place an array of thermal vias below the thermal land. ? via array size: ~4 x 9 = 36 thermal vias ? via diameter: ~0.3mm drill diameter with plated copper on the inside of each via. ? via pitch: ~1.2mm. vias should drop to and contact as much buried metal area as feasible to provide the best thermal path. thermal fault protection in the event the die temperature exceeds +170c (typ.) the output of the ldo will shut do wn until the die temperature can cool down to +150c (typ.). the le vel of power combined with the thermal impedance of the package ( jc of 5c/w for the 16 ld cdfp package) will determine if the junction temperature exceeds the thermal shutdown temperature specified in the specification table (see ?bottom metal mounting guidelines? on page 8). r ocp 893 i ocp ? = (eq. 1)
isl75052seh 9 fn8456.0 may 29, 2013 typical operating performance figure 4. line regulation vs temperature (c), v out = 2.579v, i out = 0ma figure 5a. load regulation v out = 10.17v at 25c figure 5b. load regulation v out = 10.13v at 125c figure 5c. load regulation v out = 10.22v at -55c figure 6a. load regulation v out = 2.567v at 25c figure 6b. load regulation v out = 2.571v at 125c 2.555 2.560 2.565 2.570 2.575 2.580 2.585 2.590 2.595 2.600 2.605 0 2 4 6 8 10 12 14 16 18 v in (v) v out at 25c v out at 125c v out at -55c v out (v) 10.00 10.05 10.10 10.15 10.20 10.25 10.30 10.35 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) v out (v) v in = 10.8v v in = 12v v in = 13.2v v in = 14.7v 10.00 10.05 10.10 10.15 10.20 10.25 10.30 10.35 v out (v) v in = 10.8v v in = 12v v in = 13.2v v in = 14.7v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 10.00 10.05 10.10 10.15 10.20 10.25 10.30 10.35 v out (v) v in = 10.8v v in = 12v v in = 13.2v v in = 14.7v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 2.61 v out (v) v in = 4.0v v in = 4.5v v in = 5.0v v in = 5.5v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 2.61 v out (v) v in = 10.5v v in = 12v v in = 13.2v v in = 14.7v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a)
isl75052seh 10 fn8456.0 may 29, 2013 figure 6c. load regulation v out = 2.564v at -55c figure 7a. load regulation v out = 12.75v at 25c figure 7b. load regulation v out = 12.63v at 125c figure 7c. load regulation v out = 12.7v at -55c figure 8. load step response, 25c, v in = 4.0v, v out = 2.5v, i out = 0a to 1.6a, c out = 200f, 30m figure 9. load step response, 25c, v in = 4.0v, v out = 2.5v, i out = 0.15a to 1.6a, c out = 200f, 30m typical operating performance (continued) 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 2.61 v out (v) v in = 10.5v v in = 12v v in = 13.2v v in = 14.7v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 12.50 12.55 12.60 12.65 12.70 12.75 12.80 12.85 12.90 12.95 13.00 v out (v) v in = 13.2v v in = 14.7v v in = 16.2v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 12.50 12.55 12.60 12.65 12.70 12.75 12.80 12.85 12.90 12.95 13.00 v out (v) v in = 13.2v v in = 14.7v v in = 16.2v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) 12.50 12.55 12.60 12.65 12.70 12.75 12.80 12.85 12.90 12.95 13.00 v out (v) v in = 13.2v v in = 14.7v v in = 16.2v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i out (a) v out = 20mv/div i out = 500ma/div timebase = 500s/div v out = 20mv/div i out = 500ma/div timebase = 500s/div
isl75052seh 11 fn8456.0 may 29, 2013 figure 9a. load step response, 25c, v in = 13.2v, v out = 10v, i out = 0a to 1.5a, c out = 200f, 30m figure 9b. load step response, 25c, v in = 13.2v, v out = 10v, i out = 0.15a to 1.5a, c out = 200f, 30m figure 10. gain phase plots, v in = 4v, v out = 2.5v, i out =0.2a, r comp = 22k, c comp = 1nf, c out = 200f, 30m , phase margin = 98.68, gain margin = 23.01db figure 11. gain phase plots, v in = 4v, v out = 2.5v, i out =1.5a, r comp = 22k, c comp = 1nf, c out = 200f, 30m , phase margin = 84.56, gain margin = 18.06db figure 12. psrr, v in = 4.9v, v out = 4.0v, i out =1.5a, r comp = 22k, c comp = 1nf, c out = 200f, 30m typical operating performance (continued) v out = 50mv/div i out = 500ma/div timebase = 500s/div v out = 50mv/div i out = 500ma/div timebase = 500s/div -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 500 5k 50k 500k frequency (hz) gain (db) phase () phase () gain (db) -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 500 5k 50k 500k frequency (hz) gain (db) phase () phase () gain (db) -100 -90 -80 -70 -60 -50 -40 -30 100 1k 10k 100k frequency (hz) psrr (db) 125c psrr (db) 25c psrr (db) -55c psrr (db)
isl75052seh 12 fn8456.0 may 29, 2013 figure 13. 25c start-up with enable, v in = 4v, v out = 2.5v, i out =0.1a figure 14. 25c start-up with enable, v in = 4v, v out = 2.5v, i out =1.5a figure 15. 25c shutdown with enable, v in = 4v, v out = 2.5v, i out =0.1a figure 16. 25c shutdown with enable, v in = 4v, v out = 2.5v, i out =1.5a figure 17. 25c propagation delay, v in = 4.5v, v out =4v, i out = 1.5a, en 50% to v out 5% typical operating performance (continued) v out en v in p good timebase = 1ms/div c1 to c4 = 1v/div v out en v in p good timebase = 1ms/div c1 to c4 = 1v/div v out en v in p good timebase = 5ms/div c1 to c4 = 1v/div v out en v in p good timebase = 5ms/div c1 to c4 = 1v/div v out en v in p good timebase = 200s/div
isl75052seh 13 fn8456.0 may 29, 2013 package characteristics weight of packaged device 0.59 grams (typical) lid characteristics finish: gold potential: connected to pin 13 (gnd) case isolation to any lead: 20 x 10 9 ? (min) die characteristics die dimensions 2819 m x 5638 m (111 mils x 222 mils). thickness: 304.8 m 25.4 m (12.0 mils 1 mil). interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m to 1.2m 0.12m top metallization type: alcu (99.5%/0.5%) thickness: 2.7m 0.4m sustrate type: silicon backside finish silicon assembly related information substrate potential ground additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 1074 process 0.6m bicmos junction isolated
isl75052seh 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8456.0 may 29, 2013 for additional products, see www.intersil.com/en/products.html metallization mask layout table 1. die layout x-y coordinates pad x y dx dy pin name pin# 1 1019 1021 185 450 vout 1,2 2 1249 390 185 449 vout 1,2 3 2764 1354 5508 2689 vin 3,4,5 4 3070 1030 185 450 vin 3,4,5 5 3300 399 185 450 vin 3,4,5 6 5037 256 185 185 ocp 8 7 5253 1635 185 185 vccx 9 8 5099 2436 185 185 pg 10 9 4635 2436 185 185 tmode 11 10 3824 2436 185 185 comp 12 11 2840 1660 185 450 vin 3,4,5 12 1799 2436 185 185 gnd 13 13 668 2436 185 185 en 14 14 168 2381 185 185 adj 15 15 168 1972 185 184 byp 16 16 789 1652 185 450 vout 1,2
isl75052seh 15 fn8456.0 may 29, 2013 about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change may 29, 2013 fn8456.0 initial release
isl75052seh 16 fn8456.0 may 29, 2013 package outline drawing k16.e 16 lead ceramic metal seal flatpack package rev 1, 1/12 side view top view section a-a -d- -c- seating and base plane -h- base metal pin no. 1 id area 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 bsc) 0.005 (0.13) min 0.115 (2.92) 0.085 (2.16) 0.045 (1.14) 0.026 (0.66) 0.278 (7.06) 0.262 (6.65) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) min 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 lead finish 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fi nished lead surf aces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 8. 9. notes: dimensioning and tolerancing per ansi y14.5m - 1982. dimensions: inch (mm). controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the 0.420 0.400 0.198 (5.03) 0.182 (4.62) 7 bottom metal 7. the bottom of the package is a solderable metal surface. bottom view optional pin 1 index bottom metal 0.005 (0.127) ref. offset from ceramic edge a a

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